Artificial Neural Network (ANN) training using gradient-based Levenberg & Marquardt (LM) algorithm has been implemented on FPGA for the solution of dynamic system identification problems within the scope of the study. In the implementation, IEEE 754 floating-point number format has been used because of the dynamism and sensitivity that it has provided. Mathematical approaches have been preferred to implement the activation function, which is the most critical phase of the study. ANN is tested by using input-output sample sets, which are shown or not shown to the network in the training phase, and success rates are given for every sample set. The obtained results demonstrate that implementation of FPGA-based ANN training is possible by using LM algorithm and as the result of the training, the ANN makes a good generalization.
This paper deals with a new approach to designing the micro-electronic system suitable for mass-parallel and neuronal structures realizations in which the high demand on safety and reliability is given. The presented concept is based on the FPGA platform. Authors point out various kinds of faults which can possibly occur during system cycle. Furthermore, authors introduce the Safety Core principle and define systems for which it is applicable. There are possibilities of using partial dynamic reconfiguration shown in this paper in the context of FPGA fabric testing, faults catching and correcting.
This paper describes the first attempt of hardware implementation of Multistream Compression (MSC) algorithm. The algorithm is transformed to series of Finite State Machines with Datapath using Register-Transfer methodology. Those state machines are then implemented in VHDL to selected FPGA platform. The algorithm utilizes a special tree data structure, called MSC tree. For storage purpose of the MSC tree a Left Tree Representation is introduced. Due to parallelism, the algorithm uses multiple port access to SDRAM memory.