Hardware description of digital Hopfield neural networks for solving shortest path problem

Title:

Hardware description of digital Hopfield neural networks for solving shortest path problem

Creator:

Asgari , Hajar and Kavian , Yousef S.

Identifier:

https://cdk.lib.cas.cz/client/handle/uuid:9d4f7ad3-dd1f-493d-91ed-7eb13da31ab8
uuid:9d4f7ad3-dd1f-493d-91ed-7eb13da31ab8
doi:10.14311/NNW.2014.24.013

Subject:

Hopfield neural network, shortest path problem, FPGA implementation, and VHDL

Type:

model:article and TEXT

Format:

bez média and svazek

Description:

The shortest path problem is an important issue in communication networks which is used by many practical routing protocols. The aim of this paper is to present an intelligent model based on Hopfield neural networks (HNNs) for solving shortest path problem and implement that on Field Programmable Gate Arrays (FPGAs) chips. The Cyclone Π-EP2C70F896C6 FPGA chip from ALTERA Inc. is considered for hardware implementing and VHDL language is employed for hardware description. The synthesizing results show the proposed architecture of neuron is more efficient than relevant neuron model for chip area utilization and consequently improving the maximum operating frequency and power consumption. The proposed router core is employed to find shortest paths in ring, star and mesh communication networks and the results demonstrate the efficiency and superiority of proposed core.

Language:

English

Rights:

http://creativecommons.org/publicdomain/mark/1.0/
policy:public

Source:

Neural network world: international journal on neural and mass-parallel computing and information systems | 2014 Volume:24 | Number:2

Harvested from:

CDK

Metadata only:

false